module businterface
(
input clk,
input rst_n,
input bus_wr_n,
input bus_rd_n,
input [7:0] bus_addr,
output reg [7:0] CS
);
always @(posedge clk,negedge rst_n)
begin
	if(!rst_n) begin 
		CS<=8'h0;
	end 
	else if((!bus_wr_n)||(!bus_rd_n)) begin 
		case (bus_addr) 
		8'd0: CS[0]<=1;
		8'd1: CS[1]<=1;
		8'd2: CS[2]<=1;
		8'd3: CS[3]<=1;
		8'd4: CS[4]<=1;
		8'd5: CS[5]<=1;
		8'd6: CS[6]<=1;
		8'd7: CS[7]<=1;
		default :CS<=8'h0;
		endcase 
	end 
	else 
		CS<=8'h0;
end 

endmodule 